XiangShan
RISC-V ecosystemXiangShan is a high-performance out-of-order RV64 core written in Chisel, started in 2019 at the Institute of Computing Technology of the Chinese Academy of Sciences. Its generations take lake names, from Yanqihu, taped out in 2021, to Nanhu and Kunminghu.
Overview
XiangShan is a high-performance open source RISC-V processor. Its cores implement the 64-bit RISC-V instruction set and execute instructions out of order, so the order of execution can differ from the order the program lists to keep execution units busy. The design is written in Chisel, a hardware construction language built on Scala, and released under the Mulan Permissive Software License, version 2.
The name is Chinese for Fragrant Hills, a park in western Beijing, and each generation of the design takes the name of a lake. The first generation, Yanqihu, was taped out in 2021 on a 28 nanometer process and ran at 1.3 GHz. Taping out means sending a finished design to a factory for manufacturing. Nanhu is the second generation, and Kunminghu, the third, is in active development.
History
The Institute of Computing Technology of the Chinese Academy of Sciences started XiangShan in 2019, and work on the first generation began in June 2020. Peng Cheng Laboratory carried out much of the physical design, the step that turns the logic into a layout a factory can produce.
The team presented its development methods at MICRO 2022, a major computer architecture conference. The Beijing Institute of Open Source Chip, a nonprofit founded with industry partners, now coordinates development.
Where it is used
XiangShan targets the performance of commercial application processors, the kind found in phones and servers. Researchers use it to study high-end processor design, and the project publishes its simulation, verification and performance analysis tools alongside the core.