قائمة أدوات RISC-V

Official index of ratified RISC-V ISA, profile and platform specifications from RISC-V International.

Source of the unprivileged and privileged ISA specifications.

Assembler directives, pseudo-instructions and relocation syntax.

Calling convention, register usage and ELF format used by RISC-V compilers.

Free Linux Foundation course on edX covering hands-on CPU microarchitecture design using open-source tools (TL-Verilog / Makerchip).

By MIT.

By Oakland University.

Free Linux Foundation course on edX; covers the RISC-V ISA, specifications, and ecosystem; ideal starting point for students.

By UC Irvine.

Beginner RISC-V assembly lessons with interactive figures, translated into several languages and runnable in the Lux simulator.

Interactive Jupyter-notebook-based bootcamp for learning Chisel hardware design.

Workshop repository documenting a hands-on RISC-V TL-Verilog CPU build in five days.

Wiki page with advanced Chisel hardware design examples using the Sodor RISC-V cores.

Community-contributed Chisel patterns and solutions wiki.

Community wiki documenting a structured learning path for Chisel hardware design.

Annotated reading notes on the Rocket Chip generator source code.

Open-source textbook on hardware design using Chisel, with free PDF available.

Free, open-source textbook (with PDF releases) covering RV32I assembly from first principles; actively maintained by John Winans.

RV32IM instruction reference with encoding formats, examples and pseudo-instruction expansions.

RISC-V formal ISA Specification.

Quick-reference cheatsheet for the Chisel hardware design language.

Official documentation for the Chipyard SoC design framework.

Official wiki and introduction for the Ripes RISC-V visual simulator.

Year-in-review article covering the biggest RISC-V open-source silicon milestones of 2019.

ELCE 2018 slides on bringing embedded Linux to RISC-V platforms.

Introductory learning resource for the Shakti RISC-V processor from IIT Madras.

Accessible overview of the RISC-V base ISA and its standard extensions.

Debian wiki page on RISC-V port status and build instructions.

Tutorial on writing and visualizing RV32I assembly using the Ripes simulator.

Page for the Sail ISA specification language used to formally describe RISC-V.

Page on RISC-V-related work from UC Berkeley.

Community-maintained collection of notes, links, and learning resources for RISC-V.

Live stream walkthrough of a Hello World program running on RISC-V hardware.

YouTube playlist on designing a custom 32-bit RISC CPU from scratch.

By Western Digital Corporation.

Recordings from the RISC-V Workshop held in Zurich covering ISA development and ecosystem updates.

Paper arguing for OS-managed hardware accelerator interfaces.

IEEE paper on custom hardware support for garbage collection in managed-runtime environments.

IEEE paper on compact CNN acceleration for embedded vision.

IEEE paper on integrated power-management for RISC-V vector processors.

IEEE paper on energy-efficient RISC-V vector cores with integrated DC-DC converters.

Microsoft Research whitepaper on dedicated CNN hardware acceleration.

GCC, binutils and C library build scripts for bare-metal and Linux RISC-V targets.

Online compiler that shows the RISC-V assembly GCC and Clang generate from C, C++, Rust and other languages.

Browser-based RV32IM assembler and simulator with lessons and an instruction reference.

Official RISC-V ISA simulator used as the golden reference model.

RV32IM simulator and editor that runs in the browser, used in UC Berkeley's CS61C course.

Browser-based RV32 simulator and debugger with memory and register views.

The leading open-source machine emulator and virtualizer; supports both RV32 and RV64 system and user-mode emulation.

Fastest Verilog/SystemVerilog simulator.

Framework for agile development of Chisel-based systems-on-chip.

Portable FPGA place and route tool.

Single-core microcontroller system, based on 32-bit RISC-V cores.

lowRISC SoC platform built on the Rocket RISC-V core.

Microcontroller architecture of the more recent PULP chips.

Browser-based RISC-V architecture design space exploration tool from Boston University.

Flexible Internal Representation for RTL.

RISC-V GNU Compiler Toolchain.

Chisel/Firrtl Execution Engine.

Build Fedora Gnome Desktop on RISC-V.

FPGA Tool Performance Visualization Library.

Hardware Design Language that facilitates advanced circuit generation and design reuse in Scala.

Official website for the Chisel HDL and FIRRTL compiler framework.

Formal specification of the RISC-V ISA written in Sail, adopted as the official golden model.

Architectural test suite that checks whether an implementation follows the RISC-V specification.

SystemVerilog and UVM random instruction generator for RISC-V processor verification.

Open-source formal verification framework for RISC-V processors.

Random torture test generator for RISC-V processors.

Formal verification framework for RISC-V processors.

Testing utilities for circuits written in Chisel.

SV/UVM based open-source instruction generator for RISC-V processor verification.

Unit tests for RISC-V processors.

Universal Verification Methodology (UVM) library for open-source EDA flows.

BOOM Speculative Attacks.

Automatic black box testing.

Fedora port status, images and installation guides for RISC-V boards.

Official Ubuntu images for RISC-V boards and QEMU.

FreeBSD port status and instructions for RISC-V hardware and emulators.

RISC-V boards supported by the Zephyr real-time operating system.

Open-source high-performance out-of-order RISC-V processor developed at the Institute of Computing Technology, Chinese Academy of Sciences.

Parameterizable RISC-V SoC generator from UC Berkeley.

FPGA-friendly 32-bit RISC-V implementation written in SpinalHDL.

Experimental RISC-V implementation in Verilog, fitting in a small FPGA.

Customizable, extensible MCU-class 32-bit soft-core CPU and SoC written in VHDL.

Berkeley Out-of-Order RISC-V Processor.

32-bit RISC-V system on chip for iCE40 HX8K, iCE40 UP5K and ECP5 FPGAs.

Template for building RISC-V-based SoCs using open-source tools.

Simple example SoC using PicoRV32.

Complete SoC built around the Shakti RISC-V processor family from IIT Madras.

ASIC implementation of the PicoSoC PicoRV32.

RISC-V SoC implementation targeting Xilinx FPGAs.

Dynamically Allocated Neural Network (DANA) Accelerator.

PULP chip, 330 MHz, 22 nm, 3000 x 3000 um.

PULP chip, 500 MHz, 65 nm, 1252 x 1252 um.

PULP chip, 200 MHz, 65 nm, 2626 x 2626 um.

PULP chip, 500 MHz, 65 nm, 1252 x 1252 um.

PULP chip, 15 MHz, 180 nm, 7201 x 8160 um.

PULP chip, 400 MHz, 65 nm, 2626 x 2626 um.

Hardware designs, SDK documentation, flashing tools and system images for Allwinner D1 boards, in Chinese.

SiFive's Arduino-compatible RISC-V microcontroller board; an accessible entry point for bare-metal embedded programming.

Quad-core 64-bit RISC-V single-board computer that runs Debian, Ubuntu and Fedora.

BeagleBoard single-board computer based on the quad-core T-Head C910.

Low-cost RISC-V board based on the Bouffalo BL808 chip.

Documentation for Sipeed's Lichee and Maix RISC-V boards and modules.

Extremely low-cost ($5–$9) ultra-compact embedded Linux board based on a RISC-V + ARM dual-core SoC; great for IoT learning.

Board based on the RP2350, which can boot into two Hazard3 RISC-V cores in place of its Arm cores.

Espressif RISC-V microcontroller with Wi-Fi and Bluetooth Low Energy.

WCH 32-bit RISC-V microcontroller sold for a few cents per chip.

Lesson on the history of Brazilian chip manufacturing, the CEITEC factory and Brazilian RISC-V processors, with sources.

Brazilian 32-bit RISC-V microcontroller with Bluetooth Low Energy for IoT, also called u32BR, designed by UFCG, UFPR, UFSM, UnB and UFMG with federal funding.

UFMG report on the first fabricated BlueMacaw chips, in Portuguese.

Talk by Fernando Pereira of the UFMG Compilers Lab on the u32BR software development kit, in Portuguese.

Compact open source RISC-V processor for multi-processor systems-on-chip, from Brazilian researchers.

Brazilian national program that trains chip designers through residencies in microelectronics.

Instituto Eldorado announcement of a joint project on RISC-V for high-performance computing.

RISC-V International article on the RISC-V community in Brazil.

RISC-V International article on the first Chilean RISC-V tapeout, an RV32I core from Universidad Técnica Federico Santa María built with the open SKY130 process.

Research group at Universidad Industrial de Santander behind mRISCV, a 32-bit RISC-V microcontroller designed as the first Colombian system-on-chip.

eeNews Europe article on the Onchip team and the funding behind mRISCV.

Research institute that develops the XiangShan high-performance open source processor.

ISCAS lab contributing RISC-V support to compilers, emulators and Linux distributions.

Development environment and package manager for RISC-V hardware, from ISCAS.

Open source C906 and C910 RISC-V cores from Alibaba T-Head.

EU project developing European processors, including RISC-V accelerators for high-performance computing.

EU project building a European ecosystem of RISC-V processor IP and design tools.

Czech company offering customizable RISC-V processor IP and design tools.

Barcelona company designing RISC-V cores with vector units for AI workloads.

Family of open source RISC-V processors from IIT Madras.

Family of RISC-V processors designed by C-DAC for Indian industry.

Japanese RISC-V association with news and events in Japanese.

Taiwanese company licensing RISC-V processor cores.

UC Berkeley group where RISC-V was created, also home of Rocket Chip and BOOM.

Non-profit that owns and ratifies the RISC-V specifications.

Official repositories for the specifications, the Sail model and related tools.

Industry project funding RISC-V support in compilers, runtimes, distributions and kernels.

Non-profit supporting open source silicon through events, news and project hosting.

Maker of the Bluespec hardware description language and the Piccolo, Flute and Toooba cores.

Linux Foundation project developing open source hardware and design tools, including Rocket Chip.

Non-profit in Cambridge maintaining the Ibex core and the OpenTitan silicon root of trust.

Non-profit maintaining the CORE-V family of open source RISC-V cores, including CVA6.

ETH Zurich and University of Bologna platform for open source ultra-low-power cores and SoCs.

Company founded by the creators of the RISC-V ISA, publishing processor IP, SDKs and tooling.

Scala-based hardware description language and home of the VexRiscv and NaxRiscv cores.

Maintainers of the Yosys synthesis suite, nextpnr and riscv-formal.

RISC-V International calendar of summits, meetups and webinars.

Yearly European RISC-V conference.

Yearly Chinese RISC-V conference.

Open-source digital design forum covering RISC-V, FPGAs, and EDA topics.

Official RISC-V International technical forums for ISA and ecosystem discussions.

Community mailing list for users of the Chisel hardware design language.

Official RISC-V hardware development mailing list.

Official mailing list for RISC-V ISA specification development discussions.

Mailing list for educators using RISC-V in courses and academic programs.

Subreddit for RISC-V news, projects, and community discussion.

Telegram group for real-time RISC-V community chat.