VexRiscv
RISC-V ecosystemVexRiscv is a 32-bit core written in SpinalHDL. Plugins decide which pipeline stages, caches and extensions a build includes. Charles Papon created it, and LiteX uses it as its default CPU for FPGA systems on chip.
Overview
VexRiscv is a 32-bit RISC-V core written in SpinalHDL, a hardware description language built on Scala. A core is the part of a chip that executes instructions. VexRiscv targets FPGAs, chips that can be reconfigured to behave like a different circuit, and it avoids blocks tied to one manufacturer, so the same design runs on FPGAs from different vendors.
The design is assembled from plugins. A plugin adds one feature, such as a cache, a multiplier, a floating-point unit or a memory management unit, and the pipeline can have from two to more than five stages. The smallest build uses about 500 FPGA lookup tables, and a full build with a memory management unit runs Linux.
History
Charles Papon, the creator of SpinalHDL, started VexRiscv in 2017. Papon later created NaxRiscv, an out-of-order core built with the same plugin approach.
Where it is used
LiteX, a widely used framework for building FPGA systems on chip, uses VexRiscv as its default CPU. The Linux on LiteX VexRiscv project boots Linux on low-cost FPGA boards, and the core also runs Zephyr and FreeRTOS, two operating systems for embedded devices.