Ibex
RISC-V ecosystemIbex is a small 32-bit core with a two-stage pipeline, written in SystemVerilog and maintained by lowRISC. It started as zero-riscy in the PULP project at ETH Zurich, and OpenTitan uses it as its main processor.
Overview
Ibex is a small 32-bit RISC-V core written in SystemVerilog, a language for describing hardware. A core is the part of a chip that executes instructions. Ibex is designed for embedded control, the work of small processors that manage devices inside larger systems.
Ibex supports the base integer instruction set or its reduced embedded version, plus the M, C and B extensions for multiplication, compressed instructions and bit manipulation. Its configurations range from a minimal RV32EC build to faster builds with a single-cycle multiplier and memory protection. lowRISC publishes nightly test reports for it, and Ibex has gone through several tape-outs, meaning it has been manufactured in real chips.
History
Ibex began as zero-riscy, a core from the PULP platform, a research project of ETH Zurich and the University of Bologna that develops low-power processors. zero-riscy was presented in 2017 as a smaller relative of the RI5CY core. The design was then contributed to lowRISC, a nonprofit in Cambridge, United Kingdom, which renamed it Ibex and continues to develop it.
Where it is used
OpenTitan, an open source design for security chips that check the software a computer starts, uses Ibex as its processor. Ibex also appears in research chips and in designs that need a small core with a strong verification record.