csrci
pseudolyszt.net covers csrci and other RISC-V instructions in more detail.
Description
csrci clears bits in a control register from a constant. A control and status register, or CSR, holds processor state such as the trap handler address and the interrupt switches (see csrrw). The constant uimm is a number from 0 to 31 because it is stored in 5 bits. The form below clears every bit of the CSR that is 1 in uimm and leaves the other bits unchanged.
csrci csr, uimm
It is a pseudo-instruction, a readable name that the assembler rewrites into a real instruction. It becomes the instruction below, where rd is zero so the old value is discarded.
csrrci zero, csr, uimm
The line below turns the global interrupt enable off. The 8 is binary 1000, so it clears bit 3 of mstatus.
csrci mstatus, 8
See csrsi for setting bits.
Expands to
csrrci zero, csr, uimm
The assembler replaces this pseudo-instruction with the real instruction or instructions listed above.
Example
csrci mstatus, 8 # clears bit 3 of mstatus