csrsi

csrsi sets bits in a control register from a constant. A control and status register, or CSR, holds processor state such as the trap handler address and the interrupt switches (see csrrw). The constant uimm is a number from 0 to 31 because it is stored in 5 bits. The form below sets every bit of the CSR that is 1 in uimm and leaves the other bits unchanged.

csrsi csr, uimm

It is a pseudo-instruction, a readable name that the assembler rewrites into a real instruction. It becomes the instruction below, where rd is zero so the old value is discarded.

csrrsi zero, csr, uimm

The line below turns the global interrupt enable on. The 8 is binary 1000, so it sets bit 3 of mstatus.

csrsi mstatus, 8

Only bits 0 to 4 can be set this way, so bit 11 of mie needs csrs with a register. See csrci for clearing bits.