PicoRV32
RISC-V ecosystemPicoRV32 is an RV32IMC core written in Verilog and built to use as little FPGA area as possible. Claire Wolf, author of the Yosys synthesis suite, wrote it, and it often serves as a helper processor inside larger chips.
Overview
PicoRV32 is a small RISC-V core written in Verilog, a language for describing hardware. A core is the part of a chip that executes instructions. It implements RV32IMC, the 32-bit base instruction set with multiplication and compressed instructions, and can be reduced to RV32E, a version with fewer registers.
An FPGA is a chip that can be reconfigured to behave like a different circuit. On Xilinx 7-Series FPGAs, PicoRV32 uses between 750 and 2000 lookup tables, the basic logic cells of an FPGA, and runs at 250 to 450 MHz. It connects to memory through its own simple interface or through AXI4-Lite, a common on-chip bus standard, and offers optional interrupts and a co-processor interface for custom instructions.
History
Claire Wolf, the creator of the Yosys synthesis tool, published PicoRV32 in 2015. Yosys converts hardware descriptions into circuits, and PicoRV32 became a common test design for open source FPGA tools. The repository moved to the YosysHQ organization and is now archived, and the core no longer receives active development.
Where it is used
PicoRV32 serves as an auxiliary processor, a helper core that runs control tasks inside a larger FPGA design or chip. Its high clock speed lets it join existing designs at their own clock rate. PicoSoC, an example system included in the repository, runs PicoRV32 on low-cost iCE40 FPGA boards.