csrwi
pseudolyszt.net covers csrwi and other RISC-V instructions in more detail.
Description
csrwi writes a constant into a control register. A control and status register, or CSR, holds processor state such as the trap handler address and the interrupt switches (see csrrw). The constant uimm is a number from 0 to 31 because it is stored in 5 bits. The form below writes it into the CSR and discards the old value.
csrwi csr, uimm
It is a pseudo-instruction, a readable name that the assembler rewrites into a real instruction. It becomes the instruction below, where rd is zero so the old value is not read.
csrrwi zero, csr, uimm
The line below writes 0 into mie, which switches every interrupt source off.
csrwi mie, 0
A value above 31 does not fit, so a larger value goes into a register first and is written with csrw.
Expands to
csrrwi zero, csr, uimm
The assembler replaces this pseudo-instruction with the real instruction or instructions listed above.
Example
csrwi mie, 0 # mie = 0