csrs

csrs sets bits in a control register. A control and status register, or CSR, holds processor state such as the trap handler address and the interrupt switches (see csrrw). The form below sets every bit of the CSR that is 1 in rs and leaves the other bits unchanged.

csrs csr, rs

It is a pseudo-instruction, a readable name that the assembler rewrites into a real instruction. It becomes the instruction below, where rd is zero so the old value is discarded.

csrrs zero, csr, rs

Interrupts are enabled with two calls to csrs. The first sets bit 11 of mie, the external interrupt enable. The second sets bit 3 of mstatus, the global interrupt enable.

li t0, 0x800
csrs mie, t0
li t0, 8
csrs mstatus, t0

Both switches must be on before the processor takes an interrupt. The button also has its own enable register, described on the GPIO page. See csrc for clearing bits.

The RISC-V manual lists csrs and csrc as the shorthands for setting and clearing CSR bits when the old value is not needed.