csrrwi

csrrwi is csrrw with a constant in place of the source register. The i stands for immediate, a constant written into the instruction. The constant uimm is a number from 0 to 31 because it is stored in 5 bits. The old value of the CSR goes into rd and uimm is written into the CSR.

csrrwi rd, csr, uimm

The line below writes 0 into mie, which switches every interrupt source off, and leaves the previous mie in t1.

csrrwi t1, mie, 0

A value above 31 does not fit, so a larger value goes into a register first and is written with csrrw. When rd is zero the CSR is not read, which is the csrwi shorthand. See csrrw for what a CSR is.

The RISC-V manual says the immediate forms take a 5-bit unsigned value that is zero-extended, meaning padded with zeros on the left to the full register width.