csrrsi

csrrsi is csrrs with a constant mask in place of a register. The i stands for immediate, a constant written into the instruction. The constant uimm is a number from 0 to 31 because it is stored in 5 bits. The old value of the CSR goes into rd, then every bit that is 1 in uimm is set to 1 in the CSR.

csrrsi rd, csr, uimm

The line below sets bit 3 of mstatus and leaves the previous value in t1. The 8 is binary 1000.

csrrsi t1, mstatus, 8

Only bits 0 to 4 can be set this way. Bit 3 of mstatus, the global interrupt enable, fits. Bit 11 of mie, the external interrupt enable, does not, so that one needs csrrs with a register holding 0x800. When uimm is 0 the CSR is read and not written. When rd is zero the old value is discarded, which is the csrsi shorthand. See csrrs for the register form.