csrrs

csrrs reads a control register and sets bits in it. A control and status register, or CSR, holds processor state such as the trap handler address and the interrupt switches (see csrrw). The name is short for atomic read and set bits in CSR. The old value of the CSR goes into rd, then every bit that is 1 in rs1 is set to 1 in the CSR. Bits that are 0 in rs1 keep their value.

csrrs rd, csr, rs1

Register rs1 works as a mask, a pattern whose 1 bits choose which bits to change. The lines below set bit 3 of mstatus, the global interrupt enable, and leave the previous value in t1.

li t0, 8
csrrs t1, mstatus, t0

The 8 is binary 1000, so only bit 3 changes. When rs1 is zero, the CSR is read and never written, which is the csrr shorthand. When rd is zero, the old value is discarded, which is the csrs shorthand. See csrrw for the list of CSRs in this simulator and csrrc for clearing bits.

The RISC-V manual says csrrs with rs1=x0 does not write the CSR at all.