csrrci

csrrci is csrrc with a constant mask in place of a register. The i stands for immediate, a constant written into the instruction. The constant uimm is a number from 0 to 31 because it is stored in 5 bits. The old value of the CSR goes into rd, then every bit that is 1 in uimm is cleared to 0 in the CSR.

csrrci rd, csr, uimm

The line below clears bit 3 of mstatus, which turns the global interrupt enable off, and leaves the previous value in t1. The 8 is binary 1000.

csrrci t1, mstatus, 8

Only bits 0 to 4 can be cleared this way. When uimm is 0 the CSR is read and not written. When rd is zero the old value is discarded, which is the csrci shorthand. See csrrc for the register form.