csrrc

csrrc reads a control register and clears bits in it. A control and status register, or CSR, holds processor state such as the trap handler address and the interrupt switches (see csrrw). The name is short for atomic read and clear bits in CSR. The old value of the CSR goes into rd, then every bit that is 1 in rs1 is cleared to 0 in the CSR. Bits that are 0 in rs1 keep their value.

csrrc rd, csr, rs1

Register rs1 works as a mask, a pattern whose 1 bits choose which bits to change. The lines below clear bit 3 of mstatus, which turns the global interrupt enable off, and leave the previous value in t1.

li t0, 8
csrrc t1, mstatus, t0

When rs1 is zero, the CSR is read and never written. When rd is zero, the old value is discarded, which is the csrc shorthand. See csrrs for setting bits and csrrw for the list of CSRs in this simulator.

The RISC-V manual says csrrc with rs1=x0 does not write the CSR at all.