csrr

csrr reads a control register into a general register. A control and status register, or CSR, holds processor state such as the trap handler address and the cause of the last trap (see csrrw). The form below copies the value of the CSR into rd.

csrr rd, csr

The assembler treats it as a pseudo-instruction, a readable name that it rewrites into a real instruction. It becomes the instruction below. Because rs1 is zero, the CSR is read and nothing is written to it.

csrrs rd, csr, zero

A trap handler starts by reading two CSRs. mepc holds the address of the interrupted instruction and mcause holds the reason for the trap.

csrr t0, mcause

The top bit of mcause is 1 for an interrupt and 0 for an exception. The low bits are the cause code. The button interrupt in this simulator leaves 0x8000000b, which is an interrupt with code 11, the machine external interrupt.

The RISC-V manual defines csrr rd, csr as csrrs rd, csr, x0.