csrc

csrc clears bits in a control register. A control and status register, or CSR, holds processor state such as the trap handler address and the interrupt switches (see csrrw). The form below clears every bit of the CSR that is 1 in rs and leaves the other bits unchanged.

csrc csr, rs

It is a pseudo-instruction, a readable name that the assembler rewrites into a real instruction. It becomes the instruction below, where rd is zero so the old value is discarded.

csrrc zero, csr, rs

The lines below clear bit 3 of mstatus, which turns the global interrupt enable off.

li t0, 8
csrc mstatus, t0

The processor clears this bit itself when a trap starts, and mret restores it, so a handler rarely needs to. A program uses csrc to protect a short stretch of code from interrupts and then sets the bit again with csrs.