Spike

Overview

Spike is the reference simulator for the RISC-V instruction set. A simulator is a program that imitates a processor. Other implementations compare their behavior against a reference simulator, so a team building a new RISC-V chip runs the same program on its design and on Spike and checks that both finish with the same registers and memory.

Spike models harts, short for hardware threads. A hart is a unit inside a processor that runs its own stream of instructions. Spike covers the 32-bit and 64-bit base instruction sets and the standard extensions, including vectors. It also covers the machine, supervisor and user privilege modes that operating systems rely on.

History

Spike was written at UC Berkeley, where the RISC-V instruction set was designed starting in 2010, and its public repository dates from 2011. The name comes from the golden spike driven in 1869 to mark the completion of the first railroad across the United States.

RISC-V International now maintains Spike in its software organization on GitHub. New extensions usually reach Spike early, often while their specifications are still drafts, so hardware and compiler developers have a model to test against.

Where it is used

Spike is a command-line tool for engineers. Hardware teams use it to verify their designs, and compiler developers use it to test generated code. It runs ordinary C programs compiled for RISC-V, with help from the proxy kernel, a small program that forwards system calls from the simulated program to the host computer.

Sources

1. riscv-isa-sim README