Rocket Chip
RISC-V ecosystemRocket Chip generates in-order RISC-V cores and complete systems on chip from Chisel source code. SiFive based its first commercial cores on it, and Chipyard uses it as the base for its designs.
Overview
Rocket Chip is a generator for RISC-V systems on chip. A system on chip is a single chip that holds processor cores together with caches, memory controllers and connections to other devices. A generator is a program that produces a hardware design from a set of parameters, so the same code can output a small single-core design or a large multi-core one.
Its main core, Rocket, is in-order, which means it executes instructions in the order the program lists them. Rocket has a five-stage pipeline, an arrangement where each instruction passes through five steps and several instructions are in progress at the same time. It implements the 64-bit RISC-V instruction set with a memory management unit, the hardware behind virtual memory, so it can boot Linux. The design is written in Chisel, a hardware construction language built on the Scala programming language.
History
Rocket Chip comes from UC Berkeley, from the group that designed the RISC-V instruction set. Krste Asanović and colleagues described it in the 2016 technical report "The Rocket Chip Generator", and Berkeley built many research chips with it.
SiFive, a company founded by creators of RISC-V, based its first commercial cores on Rocket. CHIPS Alliance, an open hardware group of the Linux Foundation, now hosts the project.
Where it is used
Most users reach Rocket through Chipyard, a framework that combines Rocket, BOOM and other blocks into complete chips. Chipyard runs those chips in software simulation, on FPGAs or through manufacturing tools. An FPGA is a chip that can be reconfigured to behave like a different circuit, and researchers use it to test a design at real speed before manufacturing.