Litessera Lux
RISC-V ecosystemLitessera Lux is the RISC-V assembler and simulator for this site's assembly lessons. The assembler is written in JavaScript, and the execution core is C++ compiled to WebAssembly.
Overview
Litessera Lux is a RISC-V assembler and simulator built for this site's lessons. A simulator imitates a processor, which lets a program run without RISC-V hardware. Assembly is the readable text form of machine instructions, and RV32IM is the 32-bit base instruction set with the M extension for multiplication and division.
The assembler is written in JavaScript and reads the source twice. The first pass records labels and the size of each instruction. The second pass encodes instructions and fills in the addresses those labels stand for. Execution happens in a C++ core compiled to WebAssembly, a binary format that browsers run at close to native speed.
History
Lux began in 2026 as Tesserae Venus, a simulator written for this site's RISC-V lessons. It was renamed Litessera Lux in June 2026. The execution core later moved from JavaScript to C++ compiled to WebAssembly.
Where it is used
The site's RISC-V lessons run on Lux. A lesson opens with a program for the student to assemble and run, and the instruction reference documents the same RV32IM instructions.
Lux also handles embedded topics, including the ESP32 family of microcontrollers. It runs in the browser with nothing to install, so it works on managed school machines and on a student's own computer.