srli

srli

RISC-V Assembly Reference

lyszt.net covers srli and other RISC-V instructions in more detail.

Encoding format

R
31–25funct7
24–20rs2
19–15rs1
14–12funct3
11–7rd
6–0opcode
I
31–20imm[11:0]
19–15rs1
14–12funct3
11–7rd
6–0opcode
S
31–25imm[11:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:0]
6–0opcode
B
31–25imm[12,10:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:1,11]
6–0opcode
U
31–12imm[31:12]
11–7rd
6–0opcode
J
31–12imm[20,10:1,11,19:12]
11–7rd
6–0opcode

Description

srli moves bits right by a fixed amount and puts 0s in the vacated top positions. It is the constant-amount form of srl, which covers the mechanics and the zero fill. The i means immediate, a constant encoded in the instruction.

The form of srli appears below, where amount is a fixed number from 0 to 31.

srli rd, rs1, amount

A right shift halves a number once for every place moved, and the zero fill treats the value as never negative, so srli divides an unsigned number by a power of two with no remainder. The next line divides t0 by four.

srli t0, t0, 2

Combined with a masking AND, srli extracts one field from a packed value. Shift the field down to the bottom, then apply andi to keep only its bits. Reading the second byte of a word takes a right shift by 8 and an AND with 0xff.

The RISC-V manual encodes constant shifts as a specialization of the I-type format, one of the standard instruction layouts. The shift amount occupies the lower 5 bits of the immediate field, and bit 30 of the instruction distinguishes the two right shifts. srli performs a logical right shift, and 0s enter the upper bits.

srli always fills with 0s. That suits raw bit patterns and numbers that are never negative. On a signed value that may be negative, the 0s overwrite the sign marker. Signed division by a power of two uses srai. The choice between the two reflects how you read the bits of the register.

Example

li t0, -8
srli t1, t0, 1   # t1 = 2147483644 (zero-filled)