srl

srl

RISC-V Assembly Reference

lyszt.net covers srl and other RISC-V instructions in more detail.

Encoding format

R
31–25funct7
24–20rs2
19–15rs1
14–12funct3
11–7rd
6–0opcode
I
31–20imm[11:0]
19–15rs1
14–12funct3
11–7rd
6–0opcode
S
31–25imm[11:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:0]
6–0opcode
B
31–25imm[12,10:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:1,11]
6–0opcode
U
31–12imm[31:12]
11–7rd
6–0opcode
J
31–12imm[20,10:1,11,19:12]
11–7rd
6–0opcode

Description

srl moves bits to the right, the reverse of what sll does. The letters stand for shift right logical. This form takes the bits of rs1, moves them right by the count in rs2, and stores the result in rd.

srl rd, rs1, rs2

Any bits pushed past the right end are lost, and 0s fill the vacated spots on the left.

That zero fill explains the word logical. A right shift halves a value, so a shift of 1 divides by 2 and a shift of 3 divides by 8. The leftover is thrown away, matching integer division. srl divides an unsigned number by a power of two quickly.

Two right shift instructions exist, and the difference is what goes into the emptied high bits. srl puts 0s there. Its counterpart sra copies the sign bit into those positions, which preserves the sign of negative numbers. Choose srl for a raw bit pattern or a value that cannot be negative. On a signed value that may be negative, srl yields a large positive number, and sra is the correct instruction in that case.

According to the RISC-V manual, the shift count occupies the low 5 bits of register rs2. Those 5 bits span 0 through 31 places, so the remaining bits of rs2 are ignored. The manual calls srl a logical right shift, which inserts zeros at the top.

When the shift count is a constant, use the immediate form srli.

Example

li t0, -8
li t1, 1
srl t2, t0, t1   # t2 = 2147483644 (zero-filled)

References

  1. [1]RISC-V International. The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture. Version 20260120. Section 2.4.2, Integer Register-Register Instructions, page 29.
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