sra
sra
rd, rs1, rs2
rd = rs1 >> (rs2 & 31)
R
31–25funct7
24–20rs2
19–15rs1
14–12funct3
11–7rd
6–0opcode
I
31–20imm[11:0]
19–15rs1
14–12funct3
11–7rd
6–0opcode
S
31–25imm[11:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:0]
6–0opcode
B
31–25imm[12,10:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:1,11]
6–0opcode
U
31–12imm[31:12]
11–7rd
6–0opcode
J
31–12imm[20,10:1,11,19:12]
11–7rd
6–0opcode

sra is the second right shift, the partner to srl, and the difference between them is the whole reason it exists. Its name is short for shift right arithmetic. Like any right shift it slides a register's bits toward the low end and drops what falls off — sra rd, rs1, rs2 shifts rs1 right by the amount in rs2 — but it fills the vacated top positions differently.

To see why that matters, recall how negative numbers are stored. In the signed scheme RISC-V uses, the topmost bit acts as a sign marker: 1 there means the number is negative. A plain srl fills the top with 0s, which would erase that sign marker and turn a negative number into a large positive one. sra instead fills the top with copies of the existing sign bit — 1s for a negative number, 0s for a positive one. The number keeps its sign.

That makes sra the right tool for dividing a *signed* number by a power of two: shift right by 1 to halve, by 3 to divide by 8, with negatives staying negative throughout. One honest quirk: it always rounds downward (toward more negative), so -7 shifted right by 1 gives -4, whereas the div instruction would give -3. For graphics and audio work the downward rounding is usually fine.

In short: use sra for signed numbers, srl for raw bit patterns or never-negative values. For a fixed amount, use the constant form srai.