sltiu

sltiu

RISC-V Assembly Reference

lyszt.net covers sltiu and other RISC-V instructions in more detail.

Encoding format

R
31–25funct7
24–20rs2
19–15rs1
14–12funct3
11–7rd
6–0opcode
I
31–20imm[11:0]
19–15rs1
14–12funct3
11–7rd
6–0opcode
S
31–25imm[11:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:0]
6–0opcode
B
31–25imm[12,10:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:1,11]
6–0opcode
U
31–12imm[31:12]
11–7rd
6–0opcode
J
31–12imm[20,10:1,11,19:12]
11–7rd
6–0opcode

Description

sltiu combines slti and sltu. It compares a register against a constant and treats both values as unsigned. The name stacks the parts: set less than, immediate, unsigned. The form below writes 1 into rd when rs1 is below the constant imm, with both read as non-negative numbers, and 0 otherwise.

sltiu rd, rs1, imm

Unsigned, as on the sltu page, means the top bit counts as an ordinary digit of the number, so the range runs from 0 to about 4 billion. sltiu handles range checks on values that cannot be negative, such as testing whether an index is below the size of an array, in one instruction.

The line below asks whether the value is below 1.

sltiu rd, rs, 1

Zero is the only unsigned value below 1, so the result is 1 when rs is zero and 0 otherwise. This tests for equals zero, and the seqz shorthand is built from it. Equality between two values follows from it. XOR the two values, which gives zero only when they match, and test the result for zero.

The RISC-V manual says the constant is first sign-extended to 32 bits and then treated as an unsigned number. A negative constant therefore becomes a very large unsigned value. The manual gives sltiu with the constant 1 as the way to test for zero, which is the seqz pseudo-instruction.

As with slti, constants beyond the 12-bit range are loaded into a register with li and compared with sltu.

Example

li t0, -1
sltiu t1, t0, 5   # t1 = 0 (t0 read as unsigned is huge)