or

or

RISC-V Assembly Reference

lyszt.net covers or and other RISC-V instructions in more detail.

Encoding format

R
31–25funct7
24–20rs2
19–15rs1
14–12funct3
11–7rd
6–0opcode
I
31–20imm[11:0]
19–15rs1
14–12funct3
11–7rd
6–0opcode
S
31–25imm[11:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:0]
6–0opcode
B
31–25imm[12,10:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:1,11]
6–0opcode
U
31–12imm[31:12]
11–7rd
6–0opcode
J
31–12imm[20,10:1,11,19:12]
11–7rd
6–0opcode

Description

or is a bitwise instruction, so it works on the 32 bits of a register independently (the and page explains this). At a bit position the result is 1 if either input bit is 1 or both are. The result is 0 only when both inputs are 0. The form below applies this to all 32 positions of rs1 and rs2 and writes the result to rd.

or rd, rs1, rs2

OR sets bits. To turn on one bit and leave the others as they were, OR the value with a mask that has a 1 only in that position. Settings and flags packed into one register are switched on this way.

OR also merges values. When two values are shifted to positions that do not overlap, one OR combines them into a single register. Separate red, green and blue values combine into one color in the same way.

The RISC-V manual lists or among the register-register operations. It reads the source registers rs1 and rs2, performs a bitwise logical OR and writes the result to the destination register rd.

OR can only set bits to 1. Clearing a bit takes AND with a mask, and flipping a bit takes XOR. ori is the version that ORs a register with a fixed constant.

Example

li t0, 0b1100
li t1, 0b0011
or t2, t0, t1   # t2 = 0b1111

References

  1. [1]RISC-V International. The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture. Version 20260120. Section 2.4.2, Integer Register-Register Instructions, page 29.
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