mul
lyszt.net covers mul and other RISC-V instructions in more detail.
Encoding format
Description
mul multiplies two registers. It reads rs1 and rs2, multiplies those values, and writes the product to rd. The format below means rd = rs1 * rs2.
mul rd, rs1, rs2
RISC-V is organized in layers called extensions. Multiply and divide belong to the extension named M, which the smallest RISC-V core can omit. This simulator includes it, because its full name RV32IM ends in M, so mul and div are available. A processor without M must do the work in software.
The product of two 32-bit numbers can reach 64 bits, which exceeds what one register holds. mul keeps the lower 32 bits. For small values that is the whole answer. The upper 32 bits come from a separate instruction, mulh. Signed and unsigned inputs produce the same lower 32 bits, so one instruction covers both.
When both halves of a product are needed, the RISC-V manual recommends a fixed pair of instructions. A mulh instruction (or one of its unsigned variants) supplies the high half, and mul with the same source registers in the same order supplies the low half. The destination of the high half cannot be rs1 or rs2. A processor can then fuse the two instructions into one multiplication.
Multiplying by a power of two (2, 4, 8, 16 and so on) can use a left shift instead. Shifting left by 3 places multiplies by 8, and a shift costs less than a multiply (see slli). Compilers make this replacement automatically. The example multiplies 6 by 7 and leaves 42 in t2.
Example
li t0, 6 li t1, 7 mul t2, t0, t1 # t2 = 42