lw

lw

RISC-V Assembly Reference

lyszt.net covers lw and other RISC-V instructions in more detail.

Encoding format

R
31–25funct7
24–20rs2
19–15rs1
14–12funct3
11–7rd
6–0opcode
I
31–20imm[11:0]
19–15rs1
14–12funct3
11–7rd
6–0opcode
S
31–25imm[11:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:0]
6–0opcode
B
31–25imm[12,10:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:1,11]
6–0opcode
U
31–12imm[31:12]
11–7rd
6–0opcode
J
31–12imm[20,10:1,11,19:12]
11–7rd
6–0opcode

Description

lw copies a value from memory into a register. The 32 registers form the processor's small, fast working area. Memory sits alongside them as the large store: a long row of numbered slots that holds arrays, text and variables. A slot's number is its address. Computation takes place in registers, and data waits in memory between uses.

RISC-V does arithmetic on registers only, never directly on memory, so a value must be loaded into a register before use and stored back afterward. lw carries out the load. The name means load word, and a word is a 32-bit value, the width of one register.

The form of lw appears below. It takes the value in rs1, a register holding a memory address called the base, adds offset, a small constant, and reads the value at the resulting address into destination register rd.

lw rd, offset(rs1)

The next line loads the value 8 bytes past the address in t0.

lw t1, 8(t0)

The RISC-V manual calls RISC-V a load-store architecture: load and store instructions are the only ones that reach memory, and arithmetic instructions work on registers alone. The address space is 32 bits and byte-addressed, and the effective address of a load is register rs1 plus the sign-extended 12-bit offset. The execution environment, meaning the system the program runs in, decides whether memory holds the least significant byte first, called little-endian, or the most significant byte first, called big-endian. An access is naturally aligned when its address divides evenly by the size of the access, which is 4 bytes for a word. Naturally aligned accesses never raise an alignment error. A misaligned access behaves as the environment defines and can run very slowly.

The offset is there because items in memory sit at regular distances. A word is 4 bytes, so consecutive elements of an array lie 4 bytes apart, at offsets 0, 4, 8 and so on. la places the array's starting address in a register, and changing the offset reads the different elements. The example loads two neighbors of an array. Offset 0 gives the first value, 10, and offset 4 gives the next value, 20.

Example

.data
arr: .word 10, 20
.text
la t0, arr
lw t1, 0(t0)   # t1 = 10
lw t2, 4(t0)   # t2 = 20

References

  1. [1]RISC-V International. The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture. Version 20260120. Section 2.6, Load and Store Instructions, pages 33 to 34.
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