div divides one register by another. It reads source registers rs1 and rs2, divides the first by the second, and writes the result into destination register rd: div rd, rs1, rs2 means rd = rs1 / rs2. Like multiply, it belongs to the M extension of optional math instructions, which this simulator includes.

This is integer division, meaning the fractional part is thrown away rather than rounded. 7 divided by 2 gives 3, not 3.5 — the remainder (the 1 left over) simply vanishes. If you need that leftover, a companion instruction rem computes it from the same two numbers. For negative results the discarding goes toward zero, so -7 / 2 gives -3, not -4.

Division has two dangerous edge cases that on many processors would crash the program. RISC-V chose instead to never crash: dividing by zero does not halt anything — it simply returns -1 (a register with every bit set to 1) by definition. The handling is quiet, so if dividing by zero would be a bug in your logic, you must check for a zero divisor yourself before dividing; the hardware will not warn you.

A practical note: division is the slowest arithmetic a processor does, often many times slower than multiplication. When dividing by a power of two (2, 4, 8…), a right shift does the same job far faster (see srai). The example divides 17 by 5, and since 5 goes into 17 three whole times with 2 left over, the quotient 3 lands in t2.