bltu

bltu

RISC-V Assembly Reference

lyszt.net covers bltu and other RISC-V instructions in more detail.

Encoding format

R
31–25funct7
24–20rs2
19–15rs1
14–12funct3
11–7rd
6–0opcode
I
31–20imm[11:0]
19–15rs1
14–12funct3
11–7rd
6–0opcode
S
31–25imm[11:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:0]
6–0opcode
B
31–25imm[12,10:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:1,11]
6–0opcode
U
31–12imm[31:12]
11–7rd
6–0opcode
J
31–12imm[20,10:1,11,19:12]
11–7rd
6–0opcode

Description

bltu performs the same branch as blt but reads both registers as unsigned. The name stands for branch if less than, unsigned. The branch is taken when rs1 is below rs2, with both values read as non-negative numbers from 0 up to about 4 billion. The blt page describes the branch itself. This page explains why the unsigned reading has an instruction of its own.

The same 32 bits represent different numbers depending on whether the top bit is read as a sign or as part of the value. blt reads the bits as signed and bltu reads them as unsigned, and the two readings disagree. A register with all bits set to 1 is -1 to blt, a very small value, and the largest possible value to bltu. Choosing the wrong instruction produces a wrong answer with no error message.

bltu fits anything that cannot be negative, such as memory addresses, sizes, counts and positions. Comparing addresses with the signed blt fails once an address is large enough to have its top bit set, because the signed reading makes it negative.

The RISC-V manual notes the same range check. A signed array bound can be checked with a single bltu, since any negative index compares greater than any non-negative bound.

A single bltu checks that an index is in range, at least 0 and below the size n.

bltu i, n, ok

If i is negative, its unsigned reading is a very large number and fails the test, so one unsigned comparison catches both the too large and the negative case.

Example

li t0, 1
li t1, -1
bltu t0, t1, done   # t1 read as unsigned is huge, so jump to 'done'

References

  1. [1]RISC-V International. The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture. Version 20260120. Section 2.5.2, Conditional Branches, pages 31 to 32.
Open in Litessera Lux, the RISC-V AssemblerBuy me a coffee