bgeu

bgeu

RISC-V Assembly Reference

lyszt.net covers bgeu and other RISC-V instructions in more detail.

Encoding format

R
31–25funct7
24–20rs2
19–15rs1
14–12funct3
11–7rd
6–0opcode
I
31–20imm[11:0]
19–15rs1
14–12funct3
11–7rd
6–0opcode
S
31–25imm[11:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:0]
6–0opcode
B
31–25imm[12,10:5]
24–20rs2
19–15rs1
14–12funct3
11–7imm[4:1,11]
6–0opcode
U
31–12imm[31:12]
11–7rd
6–0opcode
J
31–12imm[20,10:1,11,19:12]
11–7rd
6–0opcode

Description

bgeu is the unsigned version of bge and the opposite of bltu. The name is branch if greater than or equal, unsigned. It jumps to the label when rs1 is at least rs2, with both read as non-negative numbers. See bge for the comparison and bltu for what unsigned changes.

With bgeu the family has six branches. There are three questions, equal, less than and greater or equal, and the last two come in a signed and an unsigned form. beq and bne test equality, blt and bge compare signed values, and bltu and bgeu compare unsigned values. These six, together with swapping the operands for the greater than and less or equal directions, cover every comparison a program needs.

bgeu suits limits on quantities that cannot be negative. Examples are leaving a loop when a position reaches the end, rejecting an index that has reached the array size and branching to a handler when a length reaches capacity. Comparing memory addresses uses bltu and bgeu, since addresses are unsigned, and the signed versions give wrong results there.

The RISC-V manual says signed array bounds can be checked with a single unsigned branch, since any negative index compares greater than any non-negative bound. bgeu and bltu are the two forms of that check.

The line below performs the combined bounds check in one instruction.

bgeu i, n, error

It catches an index that is too large or negative, because a negative index reads as a huge unsigned value and fails the test.

Example

li t0, -1
li t1, 1
bgeu t0, t1, done   # t0 read as unsigned is huge, so jump to 'done'

References

  1. [1]RISC-V International. The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture. Version 20260120. Section 2.5.2, Conditional Branches, pages 31 to 32.
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